[1] E. R. Hsieh, W. L. Tsai, S. S. Chung et al., “The First Embedded 14nm FeFinFET NVM: 2T1CFE Array,” Symp. on VLSI Technology, Kyoto, June 13-19, 2021.
[2] W. C. Wang, C. C. Chuang, E. R. Hsieh, S. S. Chung et al., “A Novel Complementary Architecture of One-time-programmable Memory and Its Applications as Physical Unclonable Function (PUF) and One-time Password,” in IEDM Tech. Dig., San Francisco CA, Dec. 12-16, 2020.
[3] W. Y. Yang, B. Y. Chen, E. R. Hsieh, S. S. Chung et al., “Novel Concept of Hardware Security in Using Gate-switching FinFET Nonvolatile Memory to Implement True-Random-Number Generator,” in IEDM Tech. Dig., San Francisco CA, Dec. 12-16, 2020.
[4] Y. Xiao, E. R. Hsieh, S. S. Chung et al., “Novel Concept of the Transistor Variation Directed Toward the Circuit Implementation of Physical Unclonable Function (PUF) and True-random-number Generator (TRNG),” in IEDM Tech. Dig., San Francisco CA, Dec. 7-11, 2019.
[5] E. R. Hsieh, H. W. Wang, S. S. Chung et al., “Embedded PUF on 14nm HKMG FinFET Platform: A Novel 2-bit-per-cell OTP-based Memory Feasible for IoT Secuirty Solution in 5G Era,” Symp. on VLSI Technology, Kyoto, June 9-14, 2019.
[6] E. R. Hsieh, H. Y. Chang, S. S. Chung et al., “A Novel Architecture to Build Ideal-linearity Neuromorphic Synapses on a Pure Logic FinFET Platform Featuring 2.5ns PGM-time and 1012 Endurance,” Symp. on VLSI Technology, Kyoto, June 9-14, 2019.
[7] E. R. Hsieh, C. W. Chang, S. S. Chung et al., “The Demonstration of Gate Dielectric-Fuse 4kb OTP Memory Feasible for Embedded Applications in High-K Metal-gate CMOS Generations and Beyond,” Symp. on VLSI Circuits, Kyoto, June 9-14, 2019.
[8] S. S. Chung., “Embedded Resistive Switching Non-Volatile Memory Technology for 28nm and Beyond High-k Metal-Gate Generations,” accepted by IEEE VLSI-TECH, 2019.
[9] J. L. Kuo, E R. Hsieh et al., “An Energy Efficient FinFET‐based Field Programmable Synapse Array (FPSA) Feasible for One‐ shot Learning on EDGE AI,” accepted by IEEE VLSI-TECH, 2018.
[10] E R. Hsieh, S. S. Chung et al., "First Demonstration of Flash RRAM on Pure CMOS Logic 14nm FinFET Platform Featuring Excellent Immunity to Sneak-path and MLC Capability, " accepted by IEEE VLSI-TECH, 2017.(highlight)
[11] E R. Hsieh, S. S. Chung et al., “A new variation plot to examine the interfacial-dipole induced work-function variation in advanced high-k metal-gate CMOS devices,” IEEE VLSI-TECH, 2016, pp.166-167.
[12] E R. Hsieh, S. S. Chung et al., “The Demonstration of Low-cost and Logic Process Fully-compatible OTP Memory on Advanced CMOS with a Newly Found Dielectric Fuse Breakdown,” IEEE IEDM, 2015, pp. 3.4.1- pp. 3.4.4.
[13] E R. Hsieh, S. S. Chung et al., “A Circuit Level Variability Prediction of Basic Logic Gates in Advanced Trigate CMOS Technology,” IEEE IEDM, 2014, pp. 12.2.1-12.2.4.
[14] E R. Hsieh, S. S. Chung et al., “The Experimental Demonstration of the BTI-induced Breakdown Path in 28nm High-k Metal Gate Technology CMOS Devices,” IEEE VLSI Symposia on Tech., 2014, pp. 12.4.1-12.4.2. (citied 7 times)
[15] E R. Hsieh, S. S. Chung et al., “Gate Current Variation: A New Theory and Practice on Investigating the off-state Leakage of Trigate MOSFETs and the Power Dissipation of SRAM,” IEEE IEDM, 2013, pp. 31.2.1-31.2.4. (citied 1 times)
[16] E R. Hsieh, S. S. Chung et al., “The Understanding of Multi-level RTN in Trigate MOSFETs through the 2D Profiling of Traps and its Impact on SRAM Performance: A New Failure Mechanism Found,” IEEE IEDM, 2012, pp. 19.2.1-19.2.4. (citied 9 times)
[17] H. M. Tsai, E R. Hsieh, S. S. Chung et al., “The Understanding of the Trap Induced Variation in Bulk Tri-gate Devices by a Novel Random Trap Trpofiling(RTP) Technique,” IEEE VLSI Symposia on TECH., 2012, pp. 189-190.(citied 5 times)
[18] E R. Hsieh, S. S. Chung et al., “A Novel and Direct Experimental Observation of the Discrete Dopant Effect in Ultra-scaled CMOS Devices,” IEEE VLSI Symposia on TECH., 2011, pp. 194-195. (citied 2 times)
[19] S. S. Chung, E R. Hsieh et al., “Design of High-Performance and Highly Reliable nMOSFETs with Embedded Si:C S/D Extension Stressor (Si:C S/DE),” IEEE VLSI Symposia on TECH., 2009. pp. 158-159. (citied 4 times)
[20] M. H. Lin, E R. Hsieh, S. S. Chung et al., “A New Observation of Strain-induced Slow Traps in Advanced CMOS Technology with Process-induced Strain Using Random Telegraph Noise Measurement,” IEEE VLSI Symposia on TECH., 2009, pp. 52-53. (citied 11 times)
[21] E R. Hsieh, S. S. Chung et al., “A New and Simple Experimental Approach to Characterizing the Carrier Transport and Reliability of Strained CMOS Devices in the Quasi-ballistic Regime,” IEEE IEDM, 2009, pp. 779-782. (citied 2 times)
[22] S. S. Chung, E R. Hsieh et al., “More Strain and Less Stress-the guideline for Developing High-end Strained CMOS Technologies with Acceptable Reliability,” IEEE IEDM, 2008, pp. 435-438. (citied 8 times)
其他會議論文 (IRPS , VLSI-TSA , SNW , IPFA , SSDM …)
[1] M. Y. Lee, C. H. Chiu, E. R. Hsieh, S. S. Chung et al., “Fin-TFET: Design of FinFET-based Tunneling FET with Face-tunneling Mechanism,” IEEE SNW (Virtual), Kyoto, June 13-, 2021.
[2] A. Gupta, C. K. Chiang, E. R. Hsieh, S. S. Chung et al., “Design of Low Voltage Vertical Channel Face-tunneling TFET Using Ge/SiGe Materials and Its SRAM Circuit Performance,” IEEE VLSI-TSA, (Virtual), Hsinchu, April 20-23, 2020.
[3] W. Y. Yang, E. R. Hsieh, S. S. Chung et al., “A Reliable Triple-Level Operation of Resistive-Gate Flash Featuring Forming-Free and High Immunity to Sneak Path,” in IEEE IRPS, (Virtual), March 21-24, 2021.
[4] W. Y. Yang, E. R. Hsieh, S. S. Chung et al., “A Self-align Gate-last Resistive Gate Switching FinFET Nonvolatile Memory Feasible for Embedded Applications,” IEEE SNW (Virtual), Hawaii, June 12-13, 2020.
[5] (Invited) S. S. Chung, “The Advances of OTP Memory for Embedded Applications in HKMG Generation and Beyond,” IEEE ICSICT, October 30- Nov. 2, 2019.
[6] F. L. Li, E. R. Hsieh, S. S. Chung et al., “A New Structure of High-performance Source/drain Coupling Negative-capacitance FET Featuring Excellent Short-channel Controllability and Near Hysteresis-free,” International Conference on Solid State Devices and Materials (SSDM), Nagoya, Japan, Sept. 2-5, 2019.
[7] Y. C. Luo, F. L. Li, E. R. Hsieh, S. S. Chung et al., “The Guideline on Designing a High Performance NC MOSFET by Matching the Gate Capacitance and Mobility Enhancement,” IEEE VLSI-TSA, Apr. 22-25, 2019.
[8] (Invited) S. S. Chung, “Resistive Switching Non-volatile Memory Feasible for 28nm and Beyond Embedded Logic CMOS Technology,” IEEE IMW, May 12-15, 2019.
[9] Y. J. Lo, E. R. Hsieh and et al., “A Novel Experimental Approach to Extracting Negative Capacitances: Newly found Negative DIBL Effect in 14nm NC-FinFET and the Way to Achieve Hysteresis-free,” SSDM, 2018.
[10] E. R. Hsieh, S. S. Chung, and et al., “A Novel ReWritable One-Time-Programming OTP (RW-OTP) Realized by Dielectric-fuse RRAM Devices Featuring Ultra-High Reliable Retention and Good Endurance for Embedded Applications, ” VLSI-TSA, 2018.
[11] E. R. Hsieh, S. S. Chung, and et al., “ A Novel Approach to Localize the Channel Temperature Induced by the Self-heating Effect in 14nm High-k Metal-gate FinFET,” EDTM, 2018.
[12] E R. Hsieh, S. S. Chung, and et al., “ The Experimental Observations of a New Dielectric-fuse Breakdown in a Bilayer-RRAM Devices to Realize the OTP Functionality,” SSDM, 2017.
[13] D. H. Huang, E R. Hsieh, and et al., “The impact of TiN barrier on the NBTI in an advanced high-k metal-gate p-channel MOSFET,” IEEE IPFA, 2017
[14] E R. Hsieh, S. S. Chung, and et al., “The issues on the power consumption of trigate FinFET: The design and manufacturing guidelines,” IEEE IPFA, 2017
[15] E R. Hsieh, S. S. Chung, and et al., “The guideline on designing face-tunneling FET for large-scale-device applications in IoT, ” IEEE SNW, 2017, pp. 3-4.
[16] E R. Hsieh, S. S. Chung, and et al., “A novel design of P-N staggered face-tunneling TFET targeting for low power and appropriate performance applications,” IEEE VLSI-TSA, 2017.
[17] E R. Hsieh, S. S. Chung, and et al., “ Geometric Variation: A Novel Approach to Examine the Surface Roughness and the Line Roughness Effects in Trigate FinFETs,” IEEE EDTM, 2017, p. 7M-3.
[18] E R. Hsieh, S. S. Chung, and et al., “Geometric Variation: A Novel Approach to Examine the SurfaceRoughness and the Line Roughness Effects in Trigate FinFETs,” IEEE EDTM, 2017, p. 7M-3.
[19] E R. Hsieh, H. T. Wang, S. S. Chung, and et al., “Experimental techniques on the understanding of the charge loss in a SONOS nitride-storage nonvolatile memory,” IEEE IPFA, 2016, p. 38.
[20] E R. Hsieh, C. Wu, S. S. Chung, and et al., “The Experimental Observation of Soft-Error Enhanced NBTI Degradation in Trigate FinFETs for the near-Cosmic Exploration of Drones,” SSDM, 2016, p. A-7-05.
[21] E R. Hsieh, C. H. Chuang, S. S. Chung, and et al., “An Innovative 1T1R Dipole Dynamic Random Access Memory(DiRAM) Featuring High Speed, ultra-low Power, and Low Voltage Operation, “ IEEE VLSI-TSA, 2016, p. 58.
[22] E R. Hsieh, P. Y. Lu, S. S. Chung, and et al., “ The RTN measurement technique on leakage path finding in advanced high-k metal gate CMOS devices, “ IEEE IPFA, 2015, p. 9-1.
[23] E R. Hsieh, Y. S. Lin, Y. B. Zhao, S. S. Chung, and et al., “Design of complementary tilt-gate TFETs with SiGe/Si and III-V integrations feasible for ultra-low-power applications, ” IEEE SNW, 2015, p. 6-2.
[24] Y. B. Zhao, E. R. Hsieh, C. H. Chien, S. S. Chung, and et al., “Design of Complementary Raised Drain Tunneling FET for Ultra-low Voltage Application,”JSAP SSDM, 2015, p. K-1-2.
[25] C. M. Huang, K. C. Li, E R. Hsieh, S.S. Chung et al., “A Comprehensive Transport Model for High Performance HEMTs Considering the Parasitic Resistance and Capacitance Effects,” IEEE SNW, 2014, p.164.
[26] P. C. Wu, E R. Hsieh, P. Y. Lu, S. S. Chung, and et al., “The observation of BTI-induced RTN traps in inversion and accumulation modes on HfO 2 high-k metal gate 28nm CMOS devices,” IEEE VLSI-TSA, 2014, p. 69. (citied 2 times)
[27] E R. Hsieh, P. C. Wu, S. S. Chung, and et al., “A New Method to Effectively Separate PBTI-induced Shallow and Deep Energy Traps in a 28nm High-k Metal Gate MOSFET,” JSAP SSDM, 2014, p. F-1-5.
[28] E R. Hsieh, P. C. Wu, S. S. Chung, and et al., “The Understanding of the Bulk Trigate MOSFETs Reliability through the Manipulation of RTN Traps,”IEEE VLSI-TSA, 2013, p. 45.
[29] E. R. Hsieh, H. M. Tsai, S. S. Chung, and et al., “New Observations on the Corner Effect and STI-Induced Effect in Trigate CMOS Devices,” JSAP, SSDM, 2013, p. 708.
[30] E R. Hsieh, S. S. Chung, and et al., “The Impact of the Carrier Transport in the Random Dopant Induced Drain Current Variation in the Saturation Regime of Advanced Strained-silicon CMOS Devices,”IEEE SNW, 2012, p.78.(citied 1 times)
[31] E R. Hsieh, S. S. Chung, and et al., “New Criteria for the RDF Induced Drain Current Variation Considering Strain and Transport Effects in Strain-silicon CMOS Devices, ”IEEE VLSI-TSA, 2012, p. 26. (citied 1 times)
[32] E. R. Hsieh, H. M. Tsai, S. S. Chung, and et al.., “ The Experimental Observation of the Process Induced Random Dopant Effect in Trigate MOSFETs” JSAP, SSDM, 2012, p. 128.
[33] E. R. Hsieh, S. S. Chung, and et al., “A Novel and Direct Measurement of the Mobility on Very Small Dimension CMOS Devices with Channel Length Down to 20nm,”JSAP SSDM, 2012, p. E-9-3.
[34] X. S. Cheng, E R. Hsieh, S. S. Chung, and et al., “Experimental Determination of the Transport Parameters in High Performance Dopant-segregated Schottky-barrier MOSFETs,” IEEE VLSI-TSA, 2011, p. 120.
[35] E R. Hsieh, S. S. Chung, and et al., “New Observations on the Physical Mechanism of the Vth-variation in Nanoscale CMOS Devices after Long-term Stress,”IEEE IRPS, 2011, pp. XT.9.1 - XT.9.2. (citied 2 times)
[36] E R. Hsieh, C. Y. Cheng, S. S. Chung, and et al., “Random Trap Fluctuation (RTF) Induced Vth Variability and the Impact on the Reliability of Strained-Silicon CMOS Devices,” JSAP SSDM, 2011, p. D-5-2.
[37] E R. Hsieh, S. S. Chung, and et al., “A New Type of Inverter with Junctionless (J-Less) Transistors,” IEEE SNW, 2010, p. P2.7. (citied 3 times)
[38] M. H. Lin, E. R. Hsieh, S. S. Chung, and et al, “The Understanding of Strain-induced Device Degradation in Advanced MOSFETs with Process-induced Strain Technology of 65nm Node and Beyond,”IEEE IRPS, 2010, p. 1053.(citied 4 times)
[39] C. H. Chang, E. R. Hsieh, S. S. Chung, and et al, “The Investigation of the Stress-induced Traps and its Correlation to PBTI in High-k dielectrics nMSOFETs by the RTN Measurement Technique,”IEEE VLSI-TSA, 2010, p. 70.
[40] C. Y. Cheng, E R. Hsieh, S. S. Chung, and et al., “The Observation of the Random Dopant Fluctuation in Strained-SOI Devices,”JSAP SSDM, 2010, p. P-3-5.
[41] E R. Hsieh, Y. H. Chu, G. D. Lee, S. S. Chung, and et al., “Separation of Interface and Bulk Traps in advanced High-k Gate Dielectric MOSFETs from a Low-Leakage Charge Pumping Technique,”JSAP SSDM, 2009, p.C-6-5L.
[42] E R. Hsieh, D. W. Chang, S. S. Chung, and et al., “The Ballistic Transport and Reliability of the SOI and Strained-SOI nMSOFETs with 65nm Node and beyond Technology,”IEEE VLSI-TSA, 2009, p. 120. (citied 1 times)
期刊論文
[1] E R. Hsieh, M. R. Jaing, J. L. Lin, S. S. Chung, T. P. Chen, S. A. Huang, T. J. Chen, and O. Cheng, "An Experimental Approach to Characterizing the Channel Local Temperature Induced by Self-Heating Effect in FinFET." IEEE J-EDS, vol. 6, pp. 866-874(2018).
[2] E Ray Hsieh, Yen Chen Kuo, Chih-Hung Cheng, Jing Ling Kuo, Meng-Ru Jiang, Jian-Li Lin, Hung-Wen Chen, Steve S Chung, Chuan-Hsi Liu, Tse Pu Chen, Shih An Huang, Tai-Ju Chen, Osbert Cheng, “A 14-nm FinFET Logic CMOS Process Compatible RRAM Flash With Excellent Immunity to Sneak Path,” IEEE, Transactions on Electron Devices, vol. 64, No. 12, pp. 4910-4918(2017). (I.F.=2.605)
[3] E R. Hsieh and S. S. Chung, “A Theory and Experimental Method to Evaluate Surface Roughness Variation of Trigate Metal Oxide Semiconductor Field Effect Transistors,”AIP, Journal of Applied Physics, vol. 119, p. 204502 (2016).
[4] E R. Hsieh and S. S. Chung, “The understanding on the evolution of stress-induced gate leakage in high-k dielectric metal-oxide-field-effect transistor by random-telegraph-noise measurement,” AIP, Applied Physic Letters, vol. 107, No. 24, p. 243506 (2015).
[5] E R. Hsieh and S. S. Chung, “The understanding of the drain-current fluctuation in a silicon-carbon source-drain strained n-channel metal-oxide-semiconductor field-effect transistors,” AIP, Applied Physic Letters, vol. 104, No. 20, p. 203503 (2014). (citied 1 times)
[6] E R. Hsieh and S. S. Chung, “The mechanisms of random trap fluctuation in metal oxide semiconductor field effect transistors,” AIP, Applied Physic Letters, vol. 101, No. 22, p. 223505 (2012). (citied 3 times)
[7] E R. Hsieh and S. S. Chung, “The proximity of the strain induced effect to improve the electron mobility in a silicon-carbon source-drain structure of n-channel metal-oxide-semiconductor field-effect transistors,” AIP,Applied Physic Letters, vol. 96, No. 9, p. 093501 (2010).(citied 14 times)
